What will computer chips look like in 2045?

“There's never been as big a shock to the semiconductor industry as the current surge in demand from AI.”

Claim: The current surge in AI demand is the largest shock the semiconductor industry has ever experienced.

“AI is driving incredible computing demand.”

Claim: AI is driving exceptionally high demand for computing.

“Easily forty to fifty percent above our maximum capacity, which I've never seen before.”

Claim: The speaker's demand is 40–50% above their maximum capacity, a level the speaker says they have never seen before.

“Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do.”

Claim: Exponentially increasing compute has driven progress in AI.

“Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do.”

Claim: Foundries will need to sustain compute growth by manufacturing more chips and increasing the capability of each chip.

“Progress in AI has been driven by exponentially increasing compute. To sustain that progress, foundries like Intel will need to manufacture far more leading-edge compute, both by producing more chips and by improving what each chip can do.”

Claim: Sustaining AI progress will require foundries such as Intel to manufacture substantially more leading-edge compute.

“But the production of these chips is bottlenecked by tools that Intel buys from their suppliers, most famously ASML's EUV machines.”

Claim: The production of advanced chips is constrained by supplier-provided tools, including ASML's EUV machines.

“If they don't have the equipment, they can't make the chips here.”

Claim: Without the necessary equipment, the speaker's organization cannot manufacture chips at its local facilities.

“Yeah, if, if-- and if we talk about 14A, 14A has actually been in development for about three-plus years at this stage. Uh, and so quite a bit of pre-work has been done to get it to the stage that it's at right now, and right now we're getting very close to where we're finalizing the process.”

Claim: Intel is close to finalizing its 14A process.

“Yeah, if, if-- and if we talk about 14A, 14A has actually been in development for about three-plus years at this stage. Uh, and so quite a bit of pre-work has been done to get it to the stage that it's at right now, and right now we're getting very close to where we're finalizing the process.”

Claim: Intel's 14A process has been in development for more than three years, with substantial preparatory work completed before its current stage.

“We're finalizing the tool sets that it will be manufactured on, and we're working on kind of the fine-tuning of each of the process steps. There's about two thousand steps in the factory that you have to go do, and you need to do really intricate work at each one of those to make sure it's fine-tuned, it can go into manufacturing, it can run thousands of wafers a week, uh, on this process, and it can be repeatable every single time.”

Claim: The 14A factory process involves about 2,000 steps, each requiring detailed tuning to enable manufacturing at thousands of wafers per week with repeatable results.

“We're finalizing the tool sets that it will be manufactured on, and we're working on kind of the fine-tuning of each of the process steps. There's about two thousand steps in the factory that you have to go do, and you need to do really intricate work at each one of those to make sure it's fine-tuned, it can go into manufacturing, it can run thousands of wafers a week, uh, on this process, and it can be repeatable every single time.”

Claim: Intel is finalizing the manufacturing tool sets for 14A and fine-tuning each of its process steps.

“Yeah, so there's a, there's a constant process that we go through in identifying defects, and there's, there's kinda two main ways that we'll identify defects. One is we have in-line metrology, so we have tools that will look at the wafers and say, "Ah, there's a defect there, there's a defect there, there's a defect there."”

Claim: Intel identifies wafer defects using in-line metrology tools.

“And then also at end of line, either e-electrical test or we sort and see where the fails are, and we will identify failures, and then we will get, uh, analysis on those failures.”

Claim: Intel detects end-of-line failures through electrical testing or sorting and then analyzes them.

“We'll cross-section it. You were in the, uh, TEM lab yesterday, and you saw how you can get cross-sections. You'll get a cross-section of a defect, and you'll-- from that you'll be able to say, "Oh, that defect is between these layers, so it must have come from this section of the flow.”

Claim: Cross-section analysis can locate a defect between layers and help identify the process-flow section where it originated.

“Oh, we have in-line metrology in that section, which has identified defects. Those are the defects we need to go after." I think what we've learned is, is that you, you don't wanna do too much innovation in one node, 'cause the more innovation that you did, the more complex it becomes.”

Claim: Introducing too much innovation in one semiconductor process node increases its complexity.

“And while that-- yeah, you'll be able to get that to work, you need to hit a certain schedule, and that's the schedule that your customer ultimately wants.”

Claim: A semiconductor process node must meet the schedule required by its customer.

“So having that predictable schedule is a key piece. So you've gotta figure out how much innovation you can put in in order to meet the customer's requirements in the timeline that they need it.”

Claim: A predictable schedule is essential, and the amount of innovation in a process node should be limited as needed to meet customer requirements on time.

“Ten nanometer was a, was a, was a good example of where we had very aggressive targets. We had-- We were doing what was called hyperscaling at the time, so we were scaling much faster than what had been historically done.”

Claim: Intel's 10-nanometer process pursued aggressive targets and hyperscaled at a pace faster than historical practice.

“In order to do that, we came up with all sorts of innovative ideas and, and, and how we could achieve that, um, without new tools because the tools weren't ready.”

Claim: Because the required tools were not ready, Intel pursued innovative approaches to meet its 10-nanometer targets without them.

“And so that put a lot of burden on the process and a lot of burden on the engineers in order to do that. Now, at the end of the day, ten-nanometer is a great technology. It has world-class yield, it has world-class performance, it has world-class cost, but it took us longer to do that than what we would have liked.”

Claim: Intel's 10-nanometer technology has world-class yield, performance, and cost, but its development took longer than Intel wanted.

“And so that put a lot of burden on the process and a lot of burden on the engineers in order to do that. Now, at the end of the day, ten-nanometer is a great technology. It has world-class yield, it has world-class performance, it has world-class cost, but it took us longer to do that than what we would have liked.”

Claim: Intel's approach to the 10-nanometer process placed substantial burden on both the process and its engineers.

“Uh, and so we've kind of tried to take that learning into future technology nodes and say, "Hey, we need to limit the amount of innovation we put in there to make sure that we keep it on schedule."”

Claim: Intel aims to limit innovation in future process nodes to help keep them on schedule, based on lessons from 10-nanometer.

“EUV was, was probably the big thing. When we started to define ten nanometer, what the conclusion was EUV was not ready.”

Claim: EUV was probably the main technology Intel should have deferred from 10-nanometer because it was considered unready when the node was defined.

“One thing that, that did also come out of ten nanometer is we started to define a set of maturity metrics.”

Claim: The team began defining technology-maturity metrics after the 10-nanometer process.

“And so we use those maturity metrics in a, in a process which you call phase gate, where we would say, to go from pathfinding into development, these are the criteria that we need to go hit.”

Claim: The team uses maturity metrics in a phase-gate process to define criteria that technologies must meet before moving from pathfinding into development.

“And there's yield criteria, defect criteria, performance criteria, and we need to hit those in order to move to the next set of the flow. And if there's something that doesn't make that, then it misses that And it goes on to the next technology, and we focus on the, the items that are ready and we can run and put into a process.”

Claim: The team's phase-gate criteria include yield, defects, and performance, and a technology must meet them to advance to the next stage of the process.

“And there's yield criteria, defect criteria, performance criteria, and we need to hit those in order to move to the next set of the flow. And if there's something that doesn't make that, then it misses that And it goes on to the next technology, and we focus on the, the items that are ready and we can run and put into a process.”

Claim: When a technology fails the phase-gate criteria, the team moves on to another technology and focuses on items ready to run and integrate into a process.

“Because one of the key things is, is staying on schedule.”

Claim: Maintaining the schedule is a key consideration in semiconductor technology development.

“Gate-all-around's a good example 'cause back in the nineties- ... we, we knew of this idea, but we knew there was these-- gonna be these problems on, on how you put this into high-volume manufacturing. And at the same time, there's other things like high K metal gate, there's, uh, strained silicon, there's FinFETs that are out there.”

Claim: By the 1990s, the industry knew about Gate-all-around transistors and anticipated challenges in bringing them into high-volume manufacturing.

“... we, we knew of this idea, but we knew there was these-- gonna be these problems on, on how you put this into high-volume manufacturing. And at the same time, there's other things like high K metal gate, there's, uh, strained silicon, there's FinFETs that are out there.”

Claim: When Gate-all-around manufacturing challenges were being considered, high-K metal gate, strained silicon, and FinFET technologies were also available.

“And so it's kinda like, when's the right time to go and tackle those?”

Claim: Choosing when to pursue each semiconductor technology was a key decision.

“Well, you don't wanna tackle something before you have to. And so if you have these other things that can drive performance, you would go and do that. We went through this path where we did this.”

Claim: The team prefers not to pursue a difficult technology prematurely and instead uses other technologies to improve performance when they can do so.

“We did strained silicon, high K metal gate, we did FinFETs, and then it became, well, we need to do things further. How do we get there? Well, Gate-all-around's really the ultimate transistor out there.”

Claim: The speaker characterizes Gate-all-around as the ultimate transistor technology.

“We did strained silicon, high K metal gate, we did FinFETs, and then it became, well, we need to do things further. How do we get there? Well, Gate-all-around's really the ultimate transistor out there.”

Claim: The team adopted strained silicon, high-K metal gate, and FinFET technologies before reaching a point where further advances were needed.

“Maybe it's time to go and start tackling some of those issues that you have. And you're right, now you have to look at how you put high K metal gate in with Gate-all-around.”

Claim: As further transistor advances became necessary, the team began addressing Gate-all-around challenges, including integrating high-K metal gate with Gate-all-around.

“Um, so it's that innovation that takes time. Sometimes it's you need new materials, sometimes it's you need a different, uh, uh, tool in order to be able to do some of the things that you need to go do.”

Claim: Semiconductor innovation takes time and may require new materials or different manufacturing tools.

“Uh, and that requires invention from the tool vendors. You have to go to the tool vendor and say, "Hey, I need a tool that can do XYZ."”

Claim: Tool vendors must invent new tools when semiconductor manufacturing requires capabilities that existing tools do not provide.

“"I need a gas that can, you know, deposit this particular material that goes into that. I need a heating chuck, uh, that has this characteristic to it."”

Claim: Semiconductor process development can require tool vendors to create specialized deposition gases or heating chucks with specified characteristics.

“Uh, all those things take time. Uh, and, and some of it's iterative, where you have to run a Gate-all-around transistor. You say, "Oh, well, that didn't work. Uh, let me figure out what was wrong with my hypothesis and try it again with some different, uh, structure."”

Claim: Developing Gate-all-around technology takes time and can involve iterative experiments in which researchers revise a failed hypothesis and test a different structure.

“If you look at the eighties and nineties, yes, it was driven really by Dennard scaling, lithography. We just make things smaller, transistors got faster, and they got more reliable, and it was very predictable cadence.”

Claim: During the 1980s and 1990s, semiconductor progress was driven mainly by Dennard scaling and lithography; shrinking transistors made them faster and more reliable on a predictable cadence.

“When we started to hit two thousands, what we saw was that's not good enough anymore. We need to do something different. And to me, it became this golden age of innovation.”

Claim: By the 2000s, the previous semiconductor-scaling approach was no longer sufficient, prompting a need for different approaches; the speaker characterized the period as a golden age of innovation.

“For each technology node, how are you gonna provide More scaling. How are you gonna provide more performance? And so it drove things like strained silicon.”

Claim: The demand for greater scaling and performance at each semiconductor technology node drove innovations such as strained silicon.

“It drove high-K metal gates. It drove FinFETs. It go- gate all around. It drove backside power. These are things that are, you know, were in the '80s and '90s, you would be like, "Oh, no, we're not touching any of that," 'cause we just continued to have the same process flow and we'd just scale it, scale it, scale it.”

Claim: The pursuit of greater scaling and performance drove the adoption of high-k metal gates, FinFETs, gate-all-around transistors, and backside power.

“You can do all sorts of things out there. You can bring in new materials. I mean, just look at the number of materials we used to use in the '90s versus the materials today. It's probably gone up 10X.”

Claim: The number of materials used in semiconductor manufacturing today has probably increased by about 10 times compared with the 1990s.

“Uh, and, and there's a lot of innovation. There's, there's atomic layer depositions. You know, I mean, just you're controlling atom by atom this stuff. So it's changed a lot how you approach the process as to before it was try to not change anything, to now it's like take the sledgehammer and start just, just tearing the thing up and come up with some, a new idea.”

Claim: Semiconductor process development has shifted from preserving existing process flows to aggressively changing them and pursuing new ideas.

“Uh, and, and there's a lot of innovation. There's, there's atomic layer depositions. You know, I mean, just you're controlling atom by atom this stuff. So it's changed a lot how you approach the process as to before it was try to not change anything, to now it's like take the sledgehammer and start just, just tearing the thing up and come up with some, a new idea.”

Claim: Atomic layer deposition enables atom-by-atom control of materials during semiconductor processing.

“Yeah. And, and, you know, High-NA's a good example of where because of the architecture of our technology versus, uh, TSMC's, we make different conclusions off of a, the same tool set.”

Claim: Intel and TSMC assess the usefulness of the same High-NA EUV tool differently because their technology architectures differ.

“We use backside power. That means that you actually alleviate some of the, uh, pitch requirements you have on the front side, and that allows you to print that directly with High-NA.”

Claim: Intel's use of backside power relaxes some front-side pitch requirements, allowing the relevant patterns to be printed directly with High-NA lithography.

“TSMC has to run very m- tighter pitches because they don't have backside power, and they can't do that with High-NA, so they have to use double patterning EUV. So for them, it's not very helpful.”

Claim: Because TSMC lacks backside power, it must use tighter pitches that cannot be printed with High-NA, requiring double-patterning EUV and making High-NA not very helpful for TSMC.

“For us, it is very helpful. Uh, now at 14 we've left it as an option, and it's something that we'll have a discussion with the customer on because there's some value proposition of it.”

Claim: High-NA lithography is very helpful for Intel.

“For us, it is very helpful. Uh, now at 14 we've left it as an option, and it's something that we'll have a discussion with the customer on because there's some value proposition of it.”

Claim: Intel has made High-NA an option for its 14A process and plans to discuss its use with customers because it offers some value proposition.

“There's some, uh, complexity that it adds.”

Claim: Using High-NA adds some complexity to the process.

“It's an option in the PDK today, and it, and we're handling it as a, as a customer by customer discussion that- ... we have as to whether or not they wanna go down that path or not.”

Claim: Intel's 14A process design kit lists High-NA as an option, with adoption handled through discussions with each customer.

“There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well. PDK is a good example of that. For decades, we've been an IDM and we've gone to our product teams and we've shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK type process.”

Claim: For decades, Intel operated as an IDM and shared transistor data directly with its product teams without a formal PDK process.

“There's definitely a learning curve to how you become a foundry, and that's something that our competitors have gone through as well. PDK is a good example of that. For decades, we've been an IDM and we've gone to our product teams and we've shown them our transistor data, and we share that data back and forth, and we haven't had a formal PDK type process.”

Claim: Becoming a foundry involves a learning curve, and Intel's competitors have also experienced it.

“So that's a new process that we've had to go, uh, implement on 18A, and 18A started out not having a PDK. And so there's definitely a lot of feedback we've got from the customers as to what they expect for quality and maturity of the PDK, what sort of information that they wanna see in there.”

Claim: Intel received customer feedback on the expected quality and maturity of its PDK and on what information it should contain.

“So that's a new process that we've had to go, uh, implement on 18A, and 18A started out not having a PDK. And so there's definitely a lot of feedback we've got from the customers as to what they expect for quality and maturity of the PDK, what sort of information that they wanna see in there.”

Claim: Intel had to implement a new PDK process for 18A, which initially did not have a PDK.

“And so we've tried to incorporate that into making sure that hey, we have a PDK that meets our customers' requirements, and I think that's where we've ended up is that we're, we're starting to get, you know, PDKs that have this.”

Claim: Intel has tried to incorporate customer requirements into its PDKs and says it is starting to produce PDKs that meet them.

“And 14A will have that from the get-go. It has very high quality PDKs. Again, there's maturity metrics for what is a PDK .5 versus a .9 versus a 1.0, and we're con- constantly going through and taking customer feedback and incorporating that into the quality of our P- PDK.”

Claim: Intel assesses PDK maturity using metrics such as versions 0.5, 0.9, and 1.0, and continually uses customer feedback to improve PDK quality.

“And 14A will have that from the get-go. It has very high quality PDKs. Again, there's maturity metrics for what is a PDK .5 versus a .9 versus a 1.0, and we're con- constantly going through and taking customer feedback and incorporating that into the quality of our P- PDK.”

Claim: Intel's 14A process will have high-quality PDKs from the outset.

“... I think, uh, where we've gotten to, you know, as far as the transistor and gate-all-around and it being the ideal transistor structure that I have, I think was somewhat inevitable.”

Claim: The speaker considers the development of the transistor and gate-all-around as an ideal transistor structure to have been somewhat inevitable.

“... about these type of things. Backside power, that one's pretty out there. Uh, I think even in the, in, in the '90s, the idea that you're gonna strip off the entire silicon substrate and put lines on the ba- backside, uh, you know, that one is probably, uh, you know, something that's a little bit out there.”

Claim: The speaker considers removing the entire silicon substrate and placing power lines on the backside to have been a far-out idea even in the 1990s.

“Um, copper, of course, copper wires are the best, so I don't know how you would end up somewhere else besides copper, I think that's pretty out there.”

Claim: The speaker considers copper wires the best and regards a complete move away from copper interconnects as far-fetched.

“I think for some of the very tightest pitches, you know, I think it's inevitable that you will replace copper, and so that's a good example of where you will have another material that will come in there.”

Claim: The speaker expects copper to be replaced by another material at the tightest interconnect pitches.

“But for the larger lines, it-- I think copper is about where it's at. I think that once you start to do gate-all-around transistors and you do backside power, now you start to enter a very different regime of-- 'cause now you see it's not, "Hey, there's just some substrate," and you stack everything on top.”

Claim: The speaker considers copper to remain the best practical choice for larger interconnect lines.

“But for the larger lines, it-- I think copper is about where it's at. I think that once you start to do gate-all-around transistors and you do backside power, now you start to enter a very different regime of-- 'cause now you see it's not, "Hey, there's just some substrate," and you stack everything on top. Now you've got a transistor which is floating an interconnect and you're like, "Okay, well, why don't I have transistors, interconnect, and then more transistors, more interconnect?"”

Claim: The speaker says gate-all-around transistors and backside power open a different design regime that makes alternating layers of transistors and interconnects conceivable.

“You know, this whole 3D stacking that we now do with just discrete chips that we stack on top of each other, now you're like, "Why can't I just build a, an entire structure like this?"”

Claim: The speaker describes current 3D stacking as stacking discrete chips and raises the possibility of building an entire structure through similar vertical integration.

“You see it with, you know, memory, NAND, DRAM, you know, they have some incredible 3D structures. NAND already does it. DRAM talks about it.”

Claim: NAND memory already uses remarkable 3D structures, while 3D structures are being discussed for DRAM.

“But I think that DRAM inevitably is gonna go there too. So a lot of people say, "Oh no, we're not gonna do this because, hey, we can't do it in the next five years." Well, come on, let's put a larger timescale on this.”

Claim: The speaker believes DRAM will inevitably adopt 3D structures.

“But I think that DRAM inevitably is gonna go there too. So a lot of people say, "Oh no, we're not gonna do this because, hey, we can't do it in the next five years." Well, come on, let's put a larger timescale on this.”

Claim: The speaker expects DRAM to eventually adopt 3D structures.

“But I think that DRAM inevitably is gonna go there too. So a lot of people say, "Oh no, we're not gonna do this because, hey, we can't do it in the next five years." Well, come on, let's put a larger timescale on this. Let's put 10 years, 20 years. In 2045, do you think you could do it? Uh, and now you start to say, "Oh yeah, I could see us having some pretty exotic structures at that point."”

Claim: The speaker argues that technology forecasts should look beyond a five-year horizon and consider possibilities 10 or 20 years out, including by 2045.

“So we limit ourselves by what we see as possible in the next four years because, you know, as I've always said, you know, when people say, "Hey, you know, how do you see technology scaling going?" It-- Yeah, we have visibility about four years, and then you get out to that four years and you go, "Yeah, I think there's something we can do another four years out of that." And you get to that four years and you're like, "Yeah, I think you can do something."”

Claim: The speaker argues that people underestimate longer-term technology progress by focusing on what seems possible within the next four years, despite being able to identify further progress at each successive four-year horizon.

“So we limit ourselves by what we see as possible in the next four years because, you know, as I've always said, you know, when people say, "Hey, you know, how do you see technology scaling going?" It-- Yeah, we have visibility about four years, and then you get out to that four years and you go, "Yeah, I think there's something we can do another four years out of that." And you get to that four years and you're like, "Yeah, I think you can do something."”

Claim: The speaker says people underestimate longer-term technology possibilities by focusing on the next four years, since reaching that horizon can reveal another four years of feasible progress.

“But if you start to talk about 10 years, yeah, it becomes hard to say what it's gonna be.”

Claim: The speaker says it is difficult to predict what technology will look like ten years in the future.

“But if you start to talk about 10 years, yeah, it becomes hard to say what it's gonna be.”

Claim: The speaker finds it difficult to say what technology will look like 10 years in the future.

“... when you try to say, "Hey, what limits compute?" Okay? It's how fast can you do the switch- ... so the frequency of the device. How much power does it take in order to do that switch, so the power efficiency of it. And the second one is how do you dissipate the heat that was generated by doing that switch, and that's the thermals piece of it.”

Claim: The speaker identifies switching frequency, switching power efficiency, and heat dissipation as three factors that limit compute.

“And I think the thermals piece is-- And, and these are not new problems. You can go back 20 years and you can see articles on these three things. And so the question is, yeah, thermals, how do you deal with that?”

Claim: The speaker says thermal challenges in computing have been discussed in articles for at least 20 years.

“Particularly when you start to talk about these 3D-type devices, I think that there is a, a need for that sort of system-level analysis and simulation tools.”

Claim: The speaker believes 3D devices require system-level analysis and simulation tools.

“I think we're at its infancy because we've just started to, to look at this. Uh, but it is a limiter, and it will be a limiter, but, you know, again, these are problems that we can go solve.”

Claim: The speaker says system-level analysis and simulation for 3D devices is at an early stage because work on it has only recently begun.

“I think we're at its infancy because we've just started to, to look at this. Uh, but it is a limiter, and it will be a limiter, but, you know, again, these are problems that we can go solve.”

Claim: The speaker says thermal issues currently limit computing and will continue to do so, although they can be solved.

“One thing you learn in this industry is that you will never have a complete data set. If you want to wait for a complete data set, you've waited too long.”

Claim: The speaker says that in the semiconductor industry a complete data set is never available, and waiting for one means a decision comes too late.

“It's already too late. So a lot of what I end up doing in those meetings is I, I decide how much risk we're gonna take on a, on a certain decision or not take on a certain decision, and you need to say, "Look, do we go now? Do we start risking production?" Because you're risking, you know, the bottom line. You're risking revenue.”

Claim: The speaker says his role in the meetings includes deciding how much risk to accept in a decision, including whether to proceed toward production despite the risk.

“Do we start risking production?" Because you're risking, you know, the bottom line. You're risking revenue.”

Claim: The speaker says that proceeding with production risks the company's bottom line and revenue.

“I, I'm, I'm worried you're, you're gonna, uh, uh, put me in the light of being an ogre 'cause I'm putting the hammer down on people But it's just- ... it's really conveying urgency.”

Claim: The speaker says that his forceful approach toward colleagues in meetings is meant to convey urgency.

“Every day counts.”

Claim: The speaker emphasizes that each day matters in the work being discussed.

“So during the deposition of our epitaxy, we get abnormal growth, a little thing like a tumor.”

Claim: The speaker says abnormal, tumor-like growth can occur during epitaxy deposition.

“Right? It's, it's going superfast.”

Claim: The speaker says the abnormal epitaxy growth proceeds very quickly.

“And that causes problems because one epi will short to the wrong epi, and, and you get, uh, uh, transistors not working. And then you gotta narrow it down to how are you gonna fix it?”

Claim: The speaker says abnormal epitaxy growth can cause an epitaxial feature to short to another and make transistors fail.

“For the past decade, Intel's chips have had this feature called processor trace. When you turn it on, it starts recording all the code your program runs, and it captures enough detail that you can go back later and reconstruct every single function call.”

Claim: Intel's processor trace records a program's executed code and enough detail to reconstruct every function call afterward.

“Most companies don't need that level of detail, but Jane Street does. They need to investigate specific fleeting moments in their trading systems, things like a delayed response to a network packet.”

Claim: Jane Street needs detailed tracing to investigate brief events in its trading systems, such as delayed responses to network packets, whereas most companies do not need that level of detail.

“Those events tend to be too brief for most debugging tools to catch. So when one of Jane Street's engineers noticed processor trace, he started playing around with it, and then he and a summer intern turned that exploration into a new tool called Magic Trace.”

Claim: A Jane Street engineer and a summer intern developed Magic Trace after the engineer experimented with Intel processor trace.

“Magic Trace leverages the output from processor trace to give Jane Street a history of every function call leading up to a specific moment of interest. This project was completely bottoms up, and it started just as something that one engineer thought would be valuable, and now traders and developers across Jane Street use Magic Trace every single day.”

Claim: Magic Trace uses processor trace output to reconstruct the function-call history leading up to a selected moment.

“Magic Trace leverages the output from processor trace to give Jane Street a history of every function call leading up to a specific moment of interest. This project was completely bottoms up, and it started just as something that one engineer thought would be valuable, and now traders and developers across Jane Street use Magic Trace every single day.”

Claim: Jane Street traders and developers use Magic Trace daily.

“Magic Trace leverages the output from processor trace to give Jane Street a history of every function call leading up to a specific moment of interest. This project was completely bottoms up, and it started just as something that one engineer thought would be valuable, and now traders and developers across Jane Street use Magic Trace every single day.”

Claim: Magic Trace originated as a bottom-up project from an engineer's idea that the tool would be valuable.

“For the most part we work highly parallel, right? So how do you decide? It's not always evident what the easiest way to fix the problem is, so you work on all the potential fixes.”

Claim: The factory's engineering work is highly parallel; when the easiest solution is unclear, teams pursue all potential fixes.

“Um, and sometimes it's not the one you expect first. Once we've identified it as a primary problem for the technology, that's where it, that this hot topics meeting gets involved, and that's how we al- align the resources into those engineering teams so that, uh, we can accelerate the work.”

Claim: After a technology problem is identified as primary, the hot topics meeting aligns engineering resources to accelerate work; the primary problem is sometimes not the one initially expected.

“So we have a tiered system of what we call hot boxes in the factory, and every grade of hot box goes a little bit faster, and it's just how the factory prioritizes that particular lot, that block of silicon that's running through the factory.”

Claim: Intel's factory uses tiers of hot boxes to prioritize lots, with higher grades moving through the factory faster.

“So our, our highest grade of hot box, hot box one, r- races through the factory. It gets priority at every single tool, but it's a drag on the entire factory.”

Claim: Hot box one receives priority at every factory tool and moves through the factory fastest, but its use slows or burdens the factory as a whole.

“If you had a, a factory person in here, they don't like using, playing that card because you're, you're ending up m- using the tools inefficiently so that you can go super, super fast.”

Claim: Factory personnel may dislike hot box one because its speed comes at the cost of inefficient tool use.

“Think of it as a highway, and you set aside that one lane for the carpool, right? Where, which everyone could use, but you're saying, "Okay, it's just the carpool." That's our hot box one. Right? Everyone clear out of that lane except for that one experiment, and that one experiment races down the highway.”

Claim: Hot box one reserves factory capacity for a single experiment, allowing it to move through quickly while other work yields priority.

“We started with wiring. A transistor is only useful once it's connected to others, and on a modern chip, that takes more than a dozen layers of metal wires stacked above the transistors called interconnect.”

Claim: Transistors need connections to other components to be useful, and modern chips use more than twelve stacked metal interconnect layers above the transistors.

“These wires are made of copper, and as they shrink, copper starts to run into trouble. Intel is exploring a replacement, ruthenium.”

Claim: As copper interconnect wires shrink, they face challenges, and Intel is exploring ruthenium as a possible replacement.

“So interestingly enough, as you scale the dimensions of those copper wires, you run into challenges. For example, copper requires typically a liner in order to deposit the copper to fill those lines.”

Claim: Scaling down copper interconnects creates challenges, including the need for a liner to deposit copper into the lines.

“Ruthenium is very different in that regard because it's a material that we can actually etch. And as such, by etching it, we don't need that liner.”

Claim: Because ruthenium can be etched, ruthenium interconnects can be made without the liner used for copper deposition.

“So now you scale those very fine dimensions, and if you can trade off that resistive liner with no liner, ruthenium starts to win.”

Claim: At very fine interconnect dimensions, ruthenium can become preferable when eliminating the liner offsets its resistivity disadvantage.

“So there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper, and that's roughly in the 20 nanometer pitch range, which means if you can i- imagine half of the pitch is your metal line and the other half is the dielectric that isolates.”

Claim: Ruthenium is expected to have better conductivity than copper beyond a crossover at approximately 20-nanometer interconnect pitch.

“The liner is, think of it almost like a glue layer or transition layer that we need in order to deposit the copper and have it stick- ... and make that connection to the copper lines below it. These are all interlocking copper lines that interconnect to each other. But every time you deposit copper, you've always had a, a liner underneath it, and in the past, that liner may have been a significant portion of the entirety of that conduction path.”

Claim: A copper liner is a glue-like transition layer that helps deposited copper adhere and connect to underlying copper lines.

“... and make that connection to the copper lines below it. These are all interlocking copper lines that interconnect to each other. But every time you deposit copper, you've always had a, a liner underneath it, and in the past, that liner may have been a significant portion of the entirety of that conduction path.”

Claim: In the past, copper liners could account for a significant share of the total conduction path.

“Uh, but over time we've scaled it, made it thinner, and so copper comes back into play as a contender.”

Claim: Thinning the liner over time has made copper a viable contender again for interconnects.

“So the integration of these materials into such a complex system as the transistor ecosystem is, uh, involves many, many different components.”

Claim: Integrating a material into a transistor ecosystem is complex and involves many components.

“The scalability is one part, but its ability to integrate is another. Uh, at the time we made a decision for cobalt, it was the forerunner. The results were stronger at the time.”

Claim: Material selection for manufacturing depends on both scalability and integration, and cobalt was selected as the leading option at the time because its results were stronger.

“But as we work with our ecosystem externally, the vendor ecosystem that provides these materials and the tools that we integrate them with, we find solutions down the road that may bring copper back in line as being, you know, the stronger of the two, and that's exactly what happens.”

Claim: Solutions developed with external material and tool vendors can later make copper a stronger option than cobalt.

“Every te- every technology that we go through, we will evaluate multiple options, and as we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision, and the leading option at the time was cobalt, now it's copper again, and perhaps in the future, it'll be ruthenium.”

Claim: Intel evaluates multiple material options for each technology and chooses a leading option as the manufacturing-ready product deadline approaches.

“Every te- every technology that we go through, we will evaluate multiple options, and as we get closer to our time horizon for delivering a manufacturing-worthy product, we have to make a decision, and the leading option at the time was cobalt, now it's copper again, and perhaps in the future, it'll be ruthenium.”

Claim: Intel's leading interconnect material option changed from cobalt to copper, and ruthenium may become the leading option in the future.

“Yeah. So that evaluation of CFET is, is currently underway. Um, not just by us, by our competition. Labs externally are looking at it.”

Claim: CFET evaluation is currently underway at the speaker’s organization, competing organizations, and external laboratories.

“It is the ultimate in stackability. We're taking transistors that had to be compressed more and more, and we're relaxing that in some ways, because we're gonna stack them on top of each other.”

Claim: CFET enables transistors to be stacked on top of one another, relaxing the need to compress them further in some ways.

“But the act of stacking does not mean that they're not interconnected. What used to be connections on the top or even on the bottom, as you've seen from our press release, now has to go vertically in between the transistors, and that's a new challenge, because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult.”

Claim: In a stacked-transistor architecture, interconnections must run vertically between transistors rather than only at the top or bottom.

“But the act of stacking does not mean that they're not interconnected. What used to be connections on the top or even on the bottom, as you've seen from our press release, now has to go vertically in between the transistors, and that's a new challenge, because the aspect ratio of creating trenches and filling those trenches becomes more and more difficult.”

Claim: Higher-aspect-ratio trenches for vertical transistor interconnections are more difficult to create and fill.

“Aspect ratio for the etches is a big part of it. We're working with our vendors to, to evolve on that. But it's also what you fill those very tiny spaces with, because filling can sometimes leave air gaps or holes that never really fill, and that's not ideal.”

Claim: Etch aspect ratio is a major challenge, and the speaker’s organization is working with vendors to improve etching capabilities.

“Aspect ratio for the etches is a big part of it. We're working with our vendors to, to evolve on that. But it's also what you fill those very tiny spaces with, because filling can sometimes leave air gaps or holes that never really fill, and that's not ideal.”

Claim: Filling very small spaces can leave unfilled air gaps or holes, which is undesirable.

“Part of the process of, of evolving these technologies, especially something more complex, like an architecture, not just a, a basic chemistry or a material, but a full architecture like CFET, is that we have to make short-loop vehicles that can give us faster turnaround.”

Claim: The speaker’s organization uses short-loop test vehicles to accelerate development of complex architectures such as CFET.

“The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through. Our goal here is to take unit cells of that process and qualify them.”

Claim: A normal semiconductor manufacturing process can take a month or longer to complete thousands of steps.

“The normal manufacturing process can take a month or longer to complete the thousands of steps that it goes through. Our goal here is to take unit cells of that process and qualify them.”

Claim: The speaker’s organization aims to qualify individual unit cells of the manufacturing process.

“So we take advantage of short-loop vehicles that can give us, you know, electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps, and once we've resolved them, then we combine them into a more complex, uh, test vehicle.”

Claim: Short-loop test vehicles provide electrical and chemical measurements for resolving development challenges, after which validated components can be combined into more complex test vehicles.

“So what you would find in here is something very simple. You might be making a diode, you might be making, uh, a capacitor, which are components of the transistor, and as those evolve and become stronger, better performing, you combine them to make the next stage, which might be the transistor itself.”

Claim: The lab develops simple components such as diodes and capacitors, improves their performance, and combines them into later stages that may include a transistor.

“So in the CFET example, you might not choose to do four ribbons on top of four ribbons. You might just choose to do one-on-one, because naturally, the aspect ratio of dealing with something that much taller becomes more and more challenging.”

Claim: The organization may test CFET with one ribbon stacked on one ribbon instead of four on four, because the taller structure creates more difficult aspect ratios.

“So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS, and that simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect.”

Claim: A simplified CFET with one NMOS wire and one PMOS wire makes it easier to evaluate device stacking and interconnection.

“Oh, absolutely. In some cases, at, at least as small.”

Claim: Some features made in the lab are at least as small as the features intended for eventual production.

“Uh, for example, you know, you've heard of 2D materials, these, uh, transition layer dichalcogenides, they're called. Uh, they're very, very thin materials. They're essentially one monolayer of atoms-”

Claim: Transition-layer dichalcogenides are very thin materials, essentially a single atomic monolayer.

“... that we deal with. Those depositions can happen in this lab. We can evaluate those films in terms of conductivity, our ability to contact them, our ability to modulate that conductivity, which is what the transistor does.”

Claim: The lab can deposit transition-layer dichalcogenide films and assess their conductivity, contactability, and conductivity modulation.

“So yes, we do have, uh, the ability to not only deposit films that are very small and thin- To the atomic scale, but also print very small features.”

Claim: The lab can deposit films at atomic-scale thicknesses and print very small features.

“We have EUV technology that can, uh, or E-beam technology that can allow us to print very small features similar to what we will eventually make in production.”

Claim: The lab’s EUV or e-beam technology can print features similar in size to those intended for eventual production.

“Um, the answer is slightly different when you're dealing with an architecture like CFET versus a novel material. Uh, materials have, of course, the challenges of, uh, being deposited, etched, removed, uh, their compatibility with other layers above and below. All those things have to be researched first before you put them in a production line. Uh, an architecture may seem like a simple evolution. Oh, you're making nanoribbon transistors next to each other.”

Claim: Before a novel material enters production, its deposition, etching, removal, and compatibility with adjacent layers must be researched.

“What's wrong with just stacking them? Um, but the act of stacking them, of course, increases the aspect ratio for etches, depositions, cleans, and the technology may simply not be ready yet.”

Claim: Transistor stacking increases aspect-ratio demands for etching, deposition, and cleaning, and the required technology may not yet be ready.

“Correct. So, so we've made a simplified version that may not be, uh, a- an advantage over our current planar t- um, side-by-side technology of nanoribbons.”

Claim: The organization’s simplified CFET may not outperform its current side-by-side nanoribbon technology.

“But we need to evolve it to make it maybe two nanoribbons, or to add the right type of metals and dielectrics in order to extract the maximum performance out of that device.”

Claim: To maximize CFET performance, the organization may need to add a second nanoribbon or use suitable metals and dielectrics.

“There's 1,000 different steps that all have to come together in a very, uh, r- unique way to make the performance compatible or actually supersede the prior technology.”

Claim: Roughly 1,000 distinct steps must work together in a specific way for a new technology to match or exceed the performance of its predecessor.

“Uh, at first, uh, you know, the first level of, uh, experiments may simply be very simple depositions and you say, "Okay, I can deposit the film, I can look at it, I can measure it," but the moment I try to make a contact to it, nothing sticks. It could be something fundamental as simple as the adhesion of the next step in the process simply has no way to adhere to the material. So you may rule out a material because of something as simple as that. Uh, more complex, uh, challenges might be, uh, the subsequent processing may have gaseous interactions with downstream steps.”

Claim: A material may be ruled out if a subsequent processing step cannot adhere to it.

“So you may rule out a material because of something as simple as that. Uh, more complex, uh, challenges might be, uh, the subsequent processing may have gaseous interactions with downstream steps. So for example, I've deposited the film, I've capped it with other materials, but they're not hermetic, and so my third or fourth or fifth step in the process may actually still interact with it and change its properties.”

Claim: If caps over a deposited film are not hermetic, later processing steps may interact with the film and change its properties through gaseous interactions.

“That makes it unstable, and now we have to find better hermetic sealing for that process, and if you don't find a way to control it, then it's, it's a dead end for us.”

Claim: The speaker's team considers a process a dead end if it cannot control interactions that make the material unstable.

“Stacking transistors is still in the research lab. Stacking whole chips is already in production, and it tackles a different problem: how separate chips communicate with each other.”

Claim: Transistor stacking remains at the research stage, whereas whole-chip stacking is in production and addresses communication between separate chips.

“Modern computers are divided into multiple parts, each optimized for a different task. For example, NVIDIA's Blackwell data center GPU joins two huge processor chips and surrounds them with eight stacks of high-bandwidth memory.”

Claim: NVIDIA's Blackwell data-center GPU combines two large processor chips and eight stacks of high-bandwidth memory.

“These chips have to constantly send data back and forth with each other, and in AI, the speed of that traffic, not the raw computation itself, is often what limits how fast the workload finishes.”

Claim: For AI workloads, inter-chip data-transfer speed often limits completion time more than raw computational speed.

“Imagine two chips side by side, communicating through their facing edges. If you double each chip's width and length, you'd have four times the area for circuitry but only twice the edge length for connections.”

Claim: Doubling each dimension of two side-by-side chips yields four times the circuitry area but only twice the facing-edge length available for connections.

“This is the area versus perimeter problem. As transistors become denser, a chip's ability to do computations increases faster than its ability to move data around.”

Claim: Increasing transistor density raises a chip's computational capacity faster than its data-movement capacity.

“The industry has known about this problem for years, so multiple technologies have been invented to address it.”

Claim: The semiconductor industry has known about the area-versus-perimeter problem for years and has developed multiple technologies to address it.

“Once a chip is made, it still has to be connected to other chips and to the rest of the computer. That step is called packaging, and it has changed a lot in the last few decades.”

Claim: Packaging connects a completed chip to other chips and the rest of a computer, and packaging technology has changed substantially over the last few decades.

“At a high level, you can think of the evolution of packaging like this. Initially, chips were laid out side by side. Wires connecting them went out the side of one chip to another.”

Claim: Early chip packaging placed chips side by side and connected them with wires running from the side of one chip to another.

“To allow for more communication density, the industry introduced a shared piece of silicon, called an interposer, for multiple chips to sit on. A chip can talk to other chips through the wiring that runs directly through the interposer.”

Claim: An interposer is a shared piece of silicon that lets multiple chips communicate through wiring in the interposer, increasing connection density.

“This type of packaging is often called 2.5D. Another way to increase connection density is to bond chips directly to one another. This allows for shorter connections between chips, but the early versions of this idea use solder bumps, which are bulky and increase resistance.”

Claim: Direct chip-to-chip bonding can increase connection density by shortening connections, although early solder-bump versions are bulky and increase resistance.

“This type of packaging is often called 2.5D. Another way to increase connection density is to bond chips directly to one another. This allows for shorter connections between chips, but the early versions of this idea use solder bumps, which are bulky and increase resistance.”

Claim: Interposer-based chip packaging is often called 2.5D packaging.

“It would be better to skip the solder and fuse the signal wire connections of the two chips directly to each other. This is called hybrid bonding, and it is one of the technologies the semiconductor industry is investing in the most.”

Claim: Hybrid bonding directly fuses signal-wire connections between chips without solder and is among the semiconductor industry's most heavily invested-in technologies.

“Hybrid bonding works by aligning the copper interconnects of one chip with those of another. Then these chips are pushed together and heated so their interconnects expand and bridge the gap between the chips.”

Claim: Hybrid bonding aligns copper interconnects on two chips and presses and heats the chips so the interconnects expand across the gap between them.

“This process makes the insulating surfaces around the copper bond as well. And so by removing the solder bumps, you end up with much denser connections. But the reason this technology is only now entering volume manufacturing is because it took a while to iron out the alignment and defect challenges that it introduced.”

Claim: Hybrid bonding is only now entering volume manufacturing because its alignment and defect challenges took time to resolve.

“This process makes the insulating surfaces around the copper bond as well. And so by removing the solder bumps, you end up with much denser connections. But the reason this technology is only now entering volume manufacturing is because it took a while to iron out the alignment and defect challenges that it introduced.”

Claim: Hybrid bonding joins the insulating surfaces around copper interconnects as well as the interconnects themselves; eliminating solder bumps enables denser connections.

“Intel has spent over 50 years optimizing its CPUs for speed, but lots of these optimizations, like caching and branch prediction and speculative execution, reduce predictability.”

Claim: Intel has spent over 50 years optimizing CPUs for speed, and techniques including caching, branch prediction, and speculative execution reduce predictability.

“The exact same instructions can take four cycles to execute one time and 300 the next.”

Claim: Identical instructions can take four cycles to execute in one instance and 300 cycles in another.

“When you stack billions of instructions together and execute them across multiple threads and cores, these non-determinisms compound into all sorts of hard-to-reproduce bugs.”

Claim: Nondeterminism compounds across billions of instructions running on multiple threads and cores, producing hard-to-reproduce bugs.

“If you work on serious systems, you've definitely experienced this. Antithesis solved this by doing something a bit crazy. They built a one hundred percent deterministic computer.”

Claim: Antithesis built a fully deterministic computer to address nondeterminism in computing systems.

“They identified every single door in Intel's X.86 architecture where non-determinism could leak it; network packets, disk reads, temperature sensors, even time itself.”

Claim: Antithesis identified sources through which nondeterminism could enter Intel's x86 architecture, including network packets, disk reads, temperature sensors, and time.

“And they either welded each of these shut or slotted in a controlled simulation. This deterministic computer is just a foundation. On top of it, Antithesis built a testing platform that compresses years of production hardening into minutes and runs your software through thousands of parallel worlds, injecting faults and intelligently steering each one towards a one-in-a-billion failure that you'd never be able to test yourself.”

Claim: Antithesis eliminated identified sources of nondeterminism or replaced them with controlled simulations.

“And they either welded each of these shut or slotted in a controlled simulation. This deterministic computer is just a foundation. On top of it, Antithesis built a testing platform that compresses years of production hardening into minutes and runs your software through thousands of parallel worlds, injecting faults and intelligently steering each one towards a one-in-a-billion failure that you'd never be able to test yourself.”

Claim: Antithesis's testing platform compresses years of production hardening into minutes by running software in thousands of parallel worlds, injecting faults, and steering each world toward one-in-a-billion failures.

“This determinism is what's behind all the other insane Antithesis features that I've mentioned over the past few episodes. It's what lets you reproduce any bug and time travel to any point in a test run.”

Claim: Antithesis's deterministic system lets users reproduce any bug and revisit any point in a test run.

“Most importantly, it's what lets you or your agents trace every failure back to its root cause. Go to antithesis.com/thorkash to learn more.”

Claim: Antithesis's deterministic system lets users or their agents trace every failure to its root cause.

“Sure. So actually around Intel, typically, I think as you're referring to die to die, we typically call it wafer to wafer. So we actually take a full wafer and another wafer and bond them together.”

Claim: Intel typically calls the approach described as die-to-die bonding wafer-to-wafer bonding, and it bonds one full wafer to another.

“Um, that's an approach that's really popular right now in the CMOS image sensor industry, and in fact, basically dominates it. Um, and it's being looked at for other things like memory stacking, all kinds of stuff people have published ideas about.”

Claim: Wafer-to-wafer bonding is currently popular in, and effectively dominates, the CMOS image sensor industry.

“Um, that's an approach that's really popular right now in the CMOS image sensor industry, and in fact, basically dominates it. Um, and it's being looked at for other things like memory stacking, all kinds of stuff people have published ideas about.”

Claim: Researchers are considering wafer-to-wafer bonding for memory stacking and other proposed applications.

“Uh, one of the challenges with that though is that you need dies that perfectly match each other and are perfectly like, uh, left-handed and right-handed, right? So you have to be able to bond exactly one to the other. So one-to-one die size is a challenge. So if they're not the exact same design device on top and bottom, that's a problem. So wafer to wafer, it's just challenging to make sure that you have wafers that match really well in terms of the sort, right?”

Claim: Wafer-to-wafer bonding requires precisely matching dies, including compatible die sizes and corresponding layouts.

“So one-to-one die size is a challenge. So if they're not the exact same design device on top and bottom, that's a problem. So wafer to wafer, it's just challenging to make sure that you have wafers that match really well in terms of the sort, right? So sort good array here versus sort good array here. If they match exactly, good die and bad die that they all match-”

Claim: Wafer-to-wafer bonding requires wafers with closely matching die-sort patterns, making it challenging to pair them successfully.

“I think we're gonna do both. We definitely have the capability to do both. It's really customer and architecture-driven, but certainly chipped wafer in the logic-to-logic space makes a lot of sense.”

Claim: The speaker expects their organization to use both wafer-level and chip-level hybrid bonding, with the choice driven by customer needs and architecture; chip-level bonding is especially suitable for logic-to-logic applications.

“That's a wonderful question. So, you know, historically, like we were saying, fifteen years ago, first level interconnect was a hundred and thirty, a hundred and fifty micrometer pitch.”

Claim: About fifteen years before the conversation, first-level interconnect pitch was 130–150 micrometers.

“Today in HVM, we're doing twenty-five micrometer pitch in Foveros. Here we're doing sub-ten. But there's already been literature out there.”

Claim: At the time of the conversation, Foveros high-volume manufacturing uses a 25-micrometer pitch, while the speaker's current work is below 10 micrometers.

“In fact, the biggest conference every year in packaging is the IEEE ECTC conference that happens in May. And there was a paper there this year showing, uh, reliability data on a zero point four five micron pitch hybrid bonded device.”

Claim: A paper presented at the IEEE ECTC conference in the year of the conversation reported reliability data for a hybrid-bonded device with a 0.45-micrometer pitch.

“So you can imagine that's a whole another order of magnitude and density, again, from where we are right now on HVI- ... and scalability that's already been proven. So I see a long runway there.”

Claim: The 0.45-micrometer hybrid-bonding pitch represents roughly another order of magnitude in density compared with current HVI, and its scalability has already been demonstrated.

“... and scalability that's already been proven. So I see a long runway there.”

Claim: The speaker believes hybrid bonding has substantial room for further development.

“So, um, the back end of the fab, you can imagine like the few layers, the below packaging are typically around one micron to a half micron in size.”

Claim: Layers in the back end of the fab below packaging are typically approximately 0.5–1 micrometer in size.

“So if you can push packaging down to point five microns or below, we can start-- You can almost think about taking layers off the top of the die and connecting to a lower layer within the silicon to another lower layer within the silicon, right?”

Claim: If packaging pitch can be reduced to 0.5 micrometers or below, it may be possible to connect lower layers within silicon by removing layers from the top of the die.

“That's really kinda where the beauty of hybrid bonding happens. You can think someday about even having reduced interconnect layers on both sides that we can bond together and have less total, you know, IR drop between the two transistor layers.”

Claim: The speaker suggests that hybrid bonding could eventually join reduced interconnect layers on both sides and reduce total IR drop between two transistor layers.

“Ah, excellent question. So there are companies out there that are looking at it for non-AI applications, even in fact, in, uh, client devices, right? And one of the big things I think that that can help with there is, well, number one, obviously the same raw interconnect density, especially between something like a CPU and a GPU.”

Claim: Companies are exploring hybrid bonding for non-AI applications, including client devices.

“Ah, excellent question. So there are companies out there that are looking at it for non-AI applications, even in fact, in, uh, client devices, right? And one of the big things I think that that can help with there is, well, number one, obviously the same raw interconnect density, especially between something like a CPU and a GPU.”

Claim: Hybrid bonding can provide high raw interconnect density in non-AI applications, especially between components such as a CPU and GPU.

“Um, but the other one is around power, right? So like we talked about before, as you get to finer and finer interconnects, you can reduce the total power consumption in picojoules per bit for that interface.”

Claim: As interconnects become finer, power consumption per bit for the interface can decrease.

“So with hybrid bonding in those applications, you could think about that as another way that packaging can help reduce the total system power budget.”

Claim: In non-AI applications, hybrid bonding could help packaging reduce total system power consumption.

“So then that gives you lots of benefits, right? Lower power, less heat for the same benefit in terms of actual electrical performance.”

Claim: Hybrid bonding can deliver lower power consumption and less heat for the same electrical performance.

“It is a limiter. Um, so we have to make the most of the capacity that we already have installed, and we'll try to increase the output from our existing fleet of tools.”

Claim: Limited EUV-tool supply constrains production, so the organization must maximize installed capacity and seek higher output from its existing tools.

“And EUV or ASML is not the only bottleneck. It is definitely a bigger bottleneck than some of the other, uh, ch- Tools, but, but to a, to a large extent, we're seeing, uh, all equipment, uh, seeing tremendous, uh, supply, supply shortage.”

Claim: EUV equipment is a major but not the only production bottleneck, and equipment across the industry is experiencing substantial supply shortages.

“Even though there are multiple providers of other tools, uh, you know, once you lock into a process flow- ... let's say 18A, right? 18A is a mature process now, so we need a specific tool. We can't just go out, go and get a different tool for the same- ... for the same. So, so therefore, we are locked into that one tool, one supplier, a-and, um, and so we rely on that.”

Claim: After a process flow such as 18A is established, the manufacturer may be locked into specific tools and cannot freely substitute other tools.

“Yes. Actually, the way to do it, and we've been doing it and generally everybody does it, is you try to maintain as much fungibility as possible going from one node to the next node.”

Claim: Manufacturers try to preserve tool fungibility when transitioning from one process node to another in order to retain ramping flexibility.

“So let's say going from 18A to 14A, maybe you would say 80% of the tool set can be reused. And then of course 14A, for example, would require some new capabilities because it's a, it's a denser geometry, so it would require some unique tools.”

Claim: The speaker estimates that about 80% of the tool set might be reusable when moving from 18A to 14A, while 14A would require some unique tools for its denser geometry.

“Given the existing constraints, let's say you, we had to maximize the output from a, from a given footprint of tools, uh, then I think it's, it's incremental because the process today is already yielding pretty high.”

Claim: With existing constraints and a fixed tool footprint, output gains are likely to be incremental because the process already has a high yield.

“And to get, you know, if, if your yield is already pretty high, to get every 1% extra yield is, is extremely hard because it's already a finely tuned process.”

Claim: Once a manufacturing process has a high yield, each additional percentage point is extremely difficult to achieve because the process is already finely tuned.

“Uh, not 10X, but, but probably like 2X, yes.”

Claim: The semiconductor supply chain could probably support roughly twice, but not ten times, the current leading-edge wafer production.

“Unless the re- the entire supply chain starting from, you know, the, the equipment suppliers, their suppliers, their sub-suppliers, unless everybody produces more- ... you, you, you can't increase the output collectively.”

Claim: Collective semiconductor supply-chain output cannot increase unless equipment suppliers and the suppliers and sub-suppliers beneath them all produce more.

“There's early signs that that could actually be, be happening already. Uh, the demand is just, the demand signals are just so high. Um, but I thought you, I think you were alluding to how the value is, is accumulating at the top of the technology stack.”

Claim: Early signs suggest AI labs may already be committing to buy as much semiconductor production as suppliers can provide, potentially by guaranteeing future demand.

“Which is, which is essentially what is happening is, uh, you know, we moved from a fully vertically integrated industry like 30, 40 years ago, maybe longer, to a very horizontal industry, right?”

Claim: The semiconductor industry shifted from full vertical integration about 30–40 years ago, or possibly earlier, to a highly horizontal structure.

“Where you know, you have foundries, you have equipment makers, you have, you know, their suppliers. And today you, you think about it, every hyperscaler is designing their own chips.”

Claim: Every hyperscaler is designing its own chips today.

“And the scale of the hyperscalers is, is so large and, and some of the, you know, the, the model companies, for example, and their demand is so high, um, yeah, they could easily just like consume an entire fab's worth of silicon on their own or, or multiple- ... fabs worth of silicon on their own. And they definitely have the, the, the, uh, capital to fund that. So in some sense we're moving from a sort of a horizontal world again to a pseudo-”

Claim: The scale and demand of hyperscalers and some model companies could allow them to consume the silicon output of one or more fabs on their own.

“... fabs worth of silicon on their own. And they definitely have the, the, the, uh, capital to fund that. So in some sense we're moving from a sort of a horizontal world again to a pseudo-”

Claim: Hyperscalers and model companies have enough capital to fund the silicon output of one or more fabs.

“... fabs worth of silicon on their own. And they definitely have the, the, the, uh, capital to fund that. So in some sense we're moving from a sort of a horizontal world again to a pseudo- ... vertical world where, where it's like the, you know, it's, it's, it's not monolithically vertically integrated, but it's kind of ver- vertically integrated, virtually vertically integrated.”

Claim: The semiconductor industry is moving from a horizontal structure toward virtual vertical integration, rather than full monolithic integration.

“That's a very important question. This entire business is, is, just relies on, on scale and, and economies of scale. I mean, if, if you look at sort of all the, uh, advanced manufacturing companies, uh, out there, probably semiconductor foundries, the scale economics is probably the purest.”

Claim: Semiconductor foundries depend heavily on economies of scale, which are probably more pronounced there than in other advanced manufacturing businesses.

“Uh, and the reason for that is the fixed cost is just so incredibly high, uh, that once you build a fab, like 80% of your cost structure is fixed.”

Claim: Once a semiconductor fab is built, roughly 80% of its cost structure is fixed because the business has very high fixed costs.

“And so what that means is every extra percentage of utilization is, is adding far more in, in sort of, uh, in revenue.”

Claim: Because fab costs are largely fixed, each additional percentage point of utilization can add disproportionately more revenue.

“So therefore, it's extremely important.”

Claim: Fab utilization is extremely important to semiconductor manufacturing economics.

“And we'll fight for every extra percent of fab utilization, but also every extra percentage of fab output. As in, you know, let's say I'm making some wafers today and the yield is like 60%, but if I improve the process and the, the die yield becomes 65% or 70%, it's, it's not a linear advantage. It's like I'm getting way more output for the given footprint, right? So there's always room to, to improve the economies of scale, and that's one of the, uh, one of the reasons why, uh, you know, you're seeing, you saw, you're seeing so much consolidation in this business, right?”

Claim: Raising die yield from 60% to 65% or 70% produces a more-than-linear increase in output from the same fab footprint.

“It's like I'm getting way more output for the given footprint, right? So there's always room to, to improve the economies of scale, and that's one of the, uh, one of the reasons why, uh, you know, you're seeing, you saw, you're seeing so much consolidation in this business, right?”

Claim: Ongoing opportunities to improve economies of scale are one reason for consolidation in the semiconductor industry.

“There's only three foundries left at the advanced node for that exact reason. And, uh, just along the way- Many companies just stop manufacturing.”

Claim: Only three foundries remain in advanced-node manufacturing, as scale economics contributed to consolidation and many companies exited manufacturing.

“Uh, I don't know if you've seen, there's a chart where like f- like forty years ago, there were like, you know, twenty foundries and, uh, you know, over time, like, the number of foundries kept d- diminishing until today there's only three.”

Claim: The number of foundries declined from about 20 around 40 years ago to three today.

“... facets. Uh, I would say the catch-up that we need to do is in scale. You know, like you said, they, they're just a much larger wafer manufacturer today than we are. Um, or and even bigger than, uh, what Samsung is. Catching up in scale will, will be a, an, a slow process and a gradual process.”

Claim: Intel expects catching up with TSMC in wafer-manufacturing scale to be a slow and gradual process.

“Uh, if you meant, you know, catch up in terms of just the technology, I think that, um, you know, I think we're, we're already there. Like, you know, we might maybe a, you know, a few percent, um, off on performance or power, uh, or, or area density, um, but, you know, in this, this sort of benchmarking of, you know, uh, somewhere one foundry is ahead or one foundry is behind, it makes sense when you're like a whole generation behind or two generations behind or ahead.”

Claim: The speaker believes Intel is already broadly at the right level technologically, although it may lag by a few percent in performance, power, or area density.

“Like, you know, we might maybe a, you know, a few percent, um, off on performance or power, uh, or, or area density, um, but, you know, in this, this sort of benchmarking of, you know, uh, somewhere one foundry is ahead or one foundry is behind, it makes sense when you're like a whole generation behind or two generations behind or ahead. Uh, that's when it makes a meaningful difference in your die output or your, you know, die area or functionality like power. But if you're within like a few percent, um, it's really, it's really, uh, you're splitting hairs at that ti- at that point in time, um, because it's, it's not very unidimensional at this point.”

Claim: The speaker argues that foundry technology comparisons matter meaningfully when the gap is a full generation or two, whereas gaps of only a few percent amount to splitting hairs.

“Uh, that's when it makes a meaningful difference in your die output or your, you know, die area or functionality like power. But if you're within like a few percent, um, it's really, it's really, uh, you're splitting hairs at that ti- at that point in time, um, because it's, it's not very unidimensional at this point. It's not just about density. It's not just about raw performance. Uh, different applications require different vectors.”

Claim: The speaker says semiconductor technology competitiveness is multidimensional because applications require different performance vectors beyond density and raw performance.

“So, you know, you can, you can be off by a few percent, but you need to be on time. Your execution needs to be such that your yields are very high to support very large and very rapid ramps.”

Claim: The speaker says that being a few percent behind on performance or area can be acceptable if a foundry executes on schedule and achieves high yields for large, rapid production ramps.

“Uh, so that's, that actually is more important than, you know, catching up on a few percent in performance or area.”

Claim: The speaker considers timely execution and high yields more important than closing a few-percent gap in performance or area.

“Yeah. First of all, I would-- I, I, I don't-- I would dispute your- ... your benchmarking. Uh, but, uh, like I said, I think, you know, uh, it's, it's important to be generally in the, in the right, right ballpark.”

Claim: The speaker disputes the interviewer’s semiconductor benchmarking but says it is important for a foundry to be generally in the right technological ballpark.

“Um, be very predictable. And also, you know, it's not unidimensional in terms of, you know, we don't build one type of transistor, let's say fourteen A or, or eighteen A. Uh, you build a few different types of transistors. There's-- Let's say there's a low leakage transistor, there's a high performance, you know, high drive current transistor.”

Claim: The speaker says a foundry’s process technology includes multiple transistor types, such as low-leakage and high-performance, high-drive-current transistors.

“You're building SRAMs. There's a high density SRAM, there's a high performance SRAM. There's many other function- functionalities like, you know, some analog circuits, RF circuits.”

Claim: The speaker says foundry technology includes high-density and high-performance SRAMs and other functions such as analog and RF circuits.

“So it's the sum of all of those that makes a technology competitive.”

Claim: The speaker says semiconductor technology competitiveness depends on the combined capabilities across transistor types, SRAM, and other circuit functions.

“Yes, very much. It's a little, um, bit of an unfair comparison between us and TSMC today, just because today they're a foundry for basically everybody, and we're largely a foundry for Intel.”

Claim: The speaker says current Intel–TSMC capital-expenditure comparisons are somewhat unfair because TSMC serves nearly everyone as a foundry, whereas Intel primarily serves Intel.

“Um, we'll become a foundry for others. Um, so in, in due course, our CapEx will also grow.”

Claim: The speaker expects Intel to serve external foundry customers and says Intel’s capital expenditures will grow over time as it does so.

“Yes. I mean, clearly, uh, in hindsight, uh, probably not the smartest time to sell off, uh, a flash memory business. There were good reasons why we did that when we did.”

Claim: The speaker says that, in hindsight, selling Intel’s flash-memory business was probably poorly timed, while acknowledging there were good reasons for the sale when it occurred.

“Um, clearly, you know, nobody could see this, this demand, uh, this, this enormous demand. Um, but, but no, today, I think, uh, I mean, essentially, the world will eat up as much compute as can possibly be made, and it'll eat, it'll eat up as much memory as can possibly be made.”

Claim: The speaker says the enormous current demand for compute and memory was not foreseeable at the time of the earlier business decisions being discussed.

“Um, clearly, you know, nobody could see this, this demand, uh, this, this enormous demand. Um, but, but no, today, I think, uh, I mean, essentially, the world will eat up as much compute as can possibly be made, and it'll eat, it'll eat up as much memory as can possibly be made.”

Claim: The speaker expects global demand to absorb as much compute and memory as can possibly be produced.

“I would argue that the, the supply crunch is larger for memory today than it is for, for compute.”

Claim: The speaker argues that the current supply crunch is more severe for memory than for compute.

“Um, unless the entire supply chain ramps up production very quickly.”

Claim: The speaker says production in 2030 will not be significantly above current forecasts unless the entire supply chain ramps up very quickly.

“I mean, we're already in the middle of '26, so there's, you know, only not, not that many years until the end of the decade. And given the lead times, you know, let's say, let's say you place a enormous order for tools today, right?”

Claim: As of mid-2026, the speaker says only a few years remain until the end of the decade.

“I mean, we're already in the middle of '26, so there's, you know, only not, not that many years until the end of the decade. And given the lead times, you know, let's say, let's say you place a enormous order for tools today, right? And you're looking at, let's say, eighteen months to get those tools. You're already into basically '28. And from that point on, if you have to build a new shell, build a new fab, I mean, you're, you're basically looking at the end of the decade.”

Claim: The speaker estimates that an enormous tool order placed in mid-2026 could take about 18 months to arrive, reaching roughly 2028.

“And you're looking at, let's say, eighteen months to get those tools. You're already into basically '28. And from that point on, if you have to build a new shell, build a new fab, I mean, you're, you're basically looking at the end of the decade.”

Claim: The speaker estimates that if a new fab shell must be built after tools arrive around 2028, the project timeline would extend to roughly the end of the decade.

“Sort of the same thinking, you know. I think he's seeing just an enormous increase in demand for, for silicon, for compute and for memory.”

Claim: The speaker believes Elon Musk sees an enormous increase in demand for silicon, compute, and memory.

“And I think he came to the conclusion that his own businesses are going to require a lot of silicon, and, uh, so he, you know, he, he thought maybe he should just do it all on his own.”

Claim: The speaker says Elon Musk concluded that his businesses would need substantial silicon and therefore considered building semiconductor manufacturing capacity himself.

“Unlike building a car, for example, um, this is such an intricate and complicated process. We thought we could work together to help accelerate his bringing up his fab.”

Claim: The speaker says Intel believed it could collaborate with Elon Musk to accelerate bringing his fab into operation.

“Unlike building a car, for example, um, this is such an intricate and complicated process. We thought we could work together to help accelerate his bringing up his fab.”

Claim: The speaker characterizes semiconductor manufacturing as an especially intricate and complicated process, contrasting it with building a car.

“Mm-hmm. It's actually not o- not just tools. I mean, there's... a fab does require a lot of power, a lot of water, like, a lot of consumables. There's many other input variables as, as well.”

Claim: A semiconductor fabrication plant requires substantial power, water, consumables, and other inputs in addition to equipment.

“Some more than others, but, but yes. Um, but yes, in, in, in one sense, yes, we need a lot more equipment, but we-- it is true, I mean, we also need a lot more just raw fab space, raw, raw clean room, uh, capacity.”

Claim: Expanding semiconductor manufacturing requires substantially more equipment and raw fab and clean-room capacity.

“Like I ex- described earlier, this is an extremely capital-heavy business, and if you look at the-- if you just plot the, you know, how much does it cost to build a fab, and if you just, over the last, I don't know, twenty, thirty, forty years, I think it's, like, doubling every four to five years.”

Claim: The speaker estimates that semiconductor fab construction costs have doubled every four to five years over roughly the past 20 to 40 years, in an extremely capital-intensive industry.

“Even inside the fab, if you look at the cost to do lithography, which is the most expensive module, uh, just patterning, that itself is doubling, like, more than that, at more than that rate, right?”

Claim: The speaker says lithography, the most expensive module in a fab, has been increasing in cost faster than the overall rate of fab construction cost increases.

“So, like, today, a high NA EUV scanner costs like-- and all its associated equipment, it's, like, four hundred million dollars, right?”

Claim: A high-NA EUV scanner together with its associated equipment costs about $400 million today.

“And so what does that mean? If that rate were to continue, if you could-- if you just look, draw the line and say, "Okay, does that mean, like, four years from now, like, cost of patterning is gonna be, like, eight hundred billion?"”

Claim: If the cost trend continues, patterning costs could reach $800 million in four years; the speaker raises this as a hypothetical extrapolation.

“Right? Doesn't, uh, you know, eight hundred million, it doesn't really make sense, right? I think that a, a very interesting thought exercise to do is to say, you know, are, are there things that could be just very radically different that we could do today, uh, that we perhaps couldn't do- ... twenty years ago? This is a very risk-averse industry for a very good reason. For exactly that reason, right? You, you put in, like, tens of billions of dollars, and you really don't want to take any risks.”

Claim: Semiconductor manufacturing is highly risk-averse because companies commit tens of billions of dollars and are reluctant to risk those investments.

“So you wanna keep doing things the way they've been done for literally decades. And this is not just true of semiconductors, but, like, everything really. Um, but if you've just kept on doing that for decade upon decade, many things just become, like, you know, you just become indoctrinated, right?”

Claim: Continuing established practices for decade after decade can cause people to become indoctrinated into treating those practices as given.

“And I mean, there are engineers who probably work at Intel who are new who just, you know, come in and they're taught, "This is how the fab-- This is the process flow," and, uh, they just take that as gospel, right?”

Claim: The speaker says new Intel engineers may be taught the established fab process flow and accept it as unquestionable.

“That that's just how it is done. But is that really the best way to build a chip today? Um, it's, it's a, it's a really valid question.”

Claim: It is a valid question whether the established semiconductor manufacturing process is still the best way to build chips today.

“Um, transistor architecture and, you know, evolving, you know, just, just the silicon transistor has continued to evolve over thirty, forty years. Um, and, uh, and that will continue. So right? You've seen the evolution from, like, the planar transistor to FinFETs to now gate-all-around transistors.”

Claim: Silicon transistor architecture has evolved over the past 30 to 40 years, and the speaker expects that evolution to continue.

“Um, and, uh, and that will continue. So right? You've seen the evolution from, like, the planar transistor to FinFETs to now gate-all-around transistors.”

Claim: The transistor architecture roadmap has progressed from planar transistors to FinFETs and then to gate-all-around transistors.

“There'll be more. Like, that roadmap is pretty, you know, it, it, it exists, and it's pretty well defined, a lot of people working on it. Um, but there's things like, you know, um, do you really need a clean room today, right? Do you need the infrastructure to be as, as sophisticated, as, as complex as it, as it is today?”

Claim: The speaker questions whether current semiconductor manufacturing requires clean rooms or infrastructure as sophisticated and complex as it is today.

“There'll be more. Like, that roadmap is pretty, you know, it, it, it exists, and it's pretty well defined, a lot of people working on it. Um, but there's things like, you know, um, do you really need a clean room today, right?”

Claim: The transistor architecture roadmap is fairly well defined and actively pursued, and the speaker expects additional developments beyond gate-all-around transistors.

“Uh, that would be a great experiment to run, but, you know, no incumbent, like, you know, Intel or TSMC or Samsung, I mean, nobody would want to just willingly do that.”

Claim: The speaker says incumbent chipmakers such as Intel, TSMC, and Samsung would not willingly test the effect of allowing people to eat and smoke in a research fab.

“Um, so, so that's what I meant really by this, you know, it's a very risk-averse business for good reason. You know, every one day lost in productivity is, like, I don't know how many dollars, right?”

Claim: A day of lost productivity in semiconductor manufacturing carries a substantial financial cost, though the speaker does not specify the amount.

“But, but, you know, it's really the risk of the, the fear of the unknown, right? So nobody is going to willingly take that risk. Um, but, uh, that's why I think, you know, in s- sometimes it's good to sort of just start with a clean slate and rethink everything, and it's like, okay, these things, you know.”

Claim: Fear of the unknown discourages people from willingly taking risks to rethink established practices, so the speaker thinks it can sometimes be beneficial to start from a clean slate.

“Uh, same thing applies to, like, you know, chip design, by the way, right? Many of the ways we do CPU design were probably, uh, locked in, like, you know, thirty years ago.”

Claim: The speaker estimates that many current CPU design practices were probably established around 30 years ago.

“Does that mean it's this smart to still do it the same way? Uh, probably not, right? Um, but, but this is a very complex problem.”

Claim: The speaker thinks it is probably not wise to continue using the same chip-design methods, while acknowledging that changing them is a very complex problem.

“You know, chip design is, like, easy to... It, it's fairly low, uh, you know, uh, l- I gu- I guess the capacity to take risk is maybe higher.”

Claim: The speaker suggests that chip design may have more capacity for risk-taking than semiconductor manufacturing.

“Uh, this one less so. But given where the economics is today, I think it's a, it's a very valid question to ask, you know. Like, maybe there's a smarter way to do this.”

Claim: Given current semiconductor economics, it is valid to ask whether there is a smarter way to manufacture chips.

“Uh, yes. I mean, no, that's a very, very valid question. Uh, had we known what we know today, we would have bought, invested more- ... like a year ago. Uh, knowing what we know now, I think we'll be investing more.”

Claim: The speaker says that if they had known a year ago what they know today, they would have invested more.

“... like a year ago. Uh, knowing what we know now, I think we'll be investing more.”

Claim: The speaker expects their organization to invest more, given what they know now.