Cadence and Synopsys have worked with TSMC and other foundries for decades on final design checks for DRC and LVS compliance.

“of some of those algorithms and is there a crude approximate way that you could do some of this you know the i think chip design is not going to change in the final sign-off for quite some time it's incredibly valuable to have cadence and synopsis who've been working with tsmc and the other foundries for decades to build the sort of you know the final check mark that says this thing is what we call drc and lvs clean”